Author

Jayanthi Srikanth

Intel Corp, NCSU - Cited by 347 - NAND Cell Process Integration

Biography

Jayanthi Srikanth  is currently working as a Professor in the Department of Community Medicine. His research interests includes Medicine. He is serving as an editorial member and reviewer of several international reputed journals. He has successfully completed his Administrative responsibilities. Jayanthi Srikanth  has authored of many research articles/books related to Community Medicine.  
Title
Cited by
Year
3D memory
J Hopkins, DF Fan, FA Simsek-Ege, J Brighten, AG Mauri, S JayantiUS Patent 8,946,807, 2015201
49
2015
Memory including blocking dielectric in etch stop tier
FA Simsek-Ege, J Hopkins, S JayantiUS Patent 9,064,970, 2015201
41
2015
Methods of fabricating semiconductor structures
S Jayanti, FA Simsek-Ege, PKR AellaUS Patent 9,275,909, 2016201
38
2016
Normally-off AlGaN/GaN-on-Si MOSHFETs with TaN floating gates and ALD SiO2tunnel dielectrics
B Lee, C Kirkpatrick, X Yang, S Jayanti, R Suri, J Roberts, V Misra2010 International Electron Devices Meeting, 20.6. 1-20.6. 4, 2010201
36
2010
Ultimate scalability of TaN metal floating gate with incorporation of high-k blocking dielectrics for flash memory applications
S Jayanti, X Yang, R Suri, V Misra2010 International Electron Devices Meeting, 5.3. 1-5.3. 4, 2010201
27
2010
Stacked thin channels for boost and leakage improvement
FA Simsek-Ege, JJ Sun, B Li, S Jayanti, H Zhao, G Huang, H LiuUS Patent 9,209,199, 2015201
27
2015
3D memory
J Hopkins, DF Fan, FA Simsek-Ege, J Brighten, AG Mauri, S JayantiUS Patent 10,170,639, 2019201
23
2019
Technique to improve performance of Al2O3 interpoly dielectric using a La2O3 interface scavenging layer for floating gate memory structures
S Jayanti, X Yang, DJ Lichtenwalner, V MisraApplied Physics Letters 96 (9), 2010201
17
2010
3D memory
J Hopkins, DF Fan, FA Simsek-Ege, J Brighten, AG Mauri, S JayantiUS Patent 9,230,986, 2016201
14
2016
Semiconductor structures including dielectric materials having differing removal rates
S Jayanti, FA Simsek-Ege, PKR AellaUS Patent 10,103,160, 2018201
11
2018
Memory including blocking dielectric in etch stop tier
FA Simsek-Ege, J Hopkins, S JayantiUS Patent ,55,10, 2017201
9
2017
Semiconductor structures including dielectric materials having differing removal rates
S Jayanti, FA Simsek-Ege, PKR AellaUS Patent 11,063,05, 2021202
9
2021
Stacked thin channels for boost and leakage improvement
FA Simsek-Ege, JJ Sun, B Li, S Jayanti, H Zhao, G Huang, H LiuUS Patent 9,412,21, 2016201
8
2016
Dual floating gate unified memory MOSFET with simultaneous dynamic and non-volatile operation
B Sarkar, N Ramanan, S Jayanti, N Di Spigna, B Lee, P Franzon, V MisraIEEE electron device letters 35 (1), 48-50, 2013201
7
2013
Memory including blocking dielectric in etch stop tier
FA Simsek-Ege, J Hopkins, S JayantiUS Patent 10,170,491, 2019201
6
2019
Investigation of Thermal Stability of High-kappa Interpoly Dielectrics in TaN Metal Floating Gate Memory Structures
S Jayanti, X Yang, V Misra2011 3rd IEEE International Memory Workshop (IMW), 1-4, 2011201
6
2011
Investigation of Thermal Stability of High-kappa Interpoly Dielectrics in TaN Metal Floating Gate Memory Structures
S Jayanti, X Yang, V Misra2011 3rd IEEE International Memory Workshop (IMW), 1-4, 2011201
6
2011
A novel double floating-gate unified memory device
N Di Spigna, D Schinke, S Jayanti, V Misra, P Franzon2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012201
4
2012
Modified floating gate and dielectric layer geometry in 3D memory arrays
R Koval, S Jayanti, H Sanda, MW Kuo, S Gowda, K ParatUS Patent 10,622,50, 2020202
4
2020
Memory including blocking dielectric in etch stop tier
FA Simsek-Ege, J Hopkins, S JayantiUS Patent 10,847,57, 000
2
2020

Referred From: https://scholar.google.com/citations?hl=en&user=uiB4gEEAAAAJ

Cited by
Citations 347
h-index 10
i10-index 10
Recommended Journals
Open Access Journals